Frequency Divider, Frequency Dividing Method Thereof, and Phase Locked Loop Utilizing the Frequency Divider

ABSTRACT

A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of, and claims priority to U.S.patent application Ser. No. 12/437,541 filed May 7, 2009, which in turnclaims priority to U.S. Provisional Application No. 61/051,685 filedSep. 5, 2008 and U.S. Provisional Application No. 61/051,682 filed Sep.5, 2008, the disclosures of which are incorporated by reference hereinin their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to frequency dividers, and moreparticularly to a frequency divider capable of reducing jitter and powerconsumption.

2. Description of the Prior Art

In many applications, a precise output frequency is often generated by afractional-N frequency divider based on a reference frequency. Whereasan integer-N frequency divider may only generate the output period as aninteger multiple of the reference period, e.g. 4 times the referenceperiod, the fractional-N frequency divider may generate fractionalmultiples of the reference period, such as 4.01 times the referenceperiod. By switching from divide by M to divide by M+1 upon detection ofa carry signal or overflow signal, the fractional-N frequency divider iscapable of synthesizing frequencies which are a fractional multiple ofthe reference frequency. For example, the fractional-N frequency dividermay output the output frequency as 0.3 times the reference frequency bydividing by 3 in two cycles of a group of three cycles, then dividing by4 in a remaining one cycle of the group of three cycles.

The fractional-N frequency divider has a complicated circuit design,which has problems of high power consumption, large chip area, andjitter performance.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided afrequency divider comprising a phase selector for receiving a pluralityof clock signals and outputting an intermediate signal corresponding tophase characteristic of at least one of the clock signals, and anadjustable delay circuit for receiving the intermediate signal andgenerating an output signal by delaying the received intermediatesignal.

A phase locked loop in one embodiment comprises a phase detector, afilter coupled to the phase detector, an oscillator coupled to thefilter, and a frequency divider coupled to the oscillator and the phasedetector. The phase detector is for detecting a phase difference betweena reference signal and an input signal, and generating a differencesignal indicating the detected phase difference. The filter is forfiltering the difference signal to generate a filtered signal. Theoscillator is for generating a plurality of clock signals based on thefiltered signal. The frequency divider is for generating afrequency-divided signal based on the clock signals, and comprises aphase selector and an adjustable delay circuit coupled to the phaseselector. The phase selector is for receiving the clock signals andoutputting an intermediate signal corresponding to phase characteristicof at least one of the clock signals. The adjustable delay circuit isfor receiving the intermediate signal and generating thefrequency-divided signal by delaying the intermediate signal. The inputsignal corresponds to the frequency-divided signal.

A frequency dividing method according to the embodiments comprisesreceiving a plurality of clock signals, generating an intermediatesignal according to phase characteristic of at least one of the clocksignals, and delaying the intermediate signal to generate afrequency-divided signal.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a frequency divider according to anembodiment of the present invention.

FIG. 2 is a diagram of a frequency divider according to one embodimentof the present invention.

FIG. 3 is a diagram of one embodiment of a pipeline delay circuit of thefrequency divider of FIG. 2.

FIG. 4 is a diagram of a first embodiment of an adjustable delay circuitof the frequency divider of FIG. 2.

FIG. 5 is a diagram of a second embodiment of the adjustable delaycircuit of the frequency divider of FIG. 2.

FIG. 6 is a diagram of a third embodiment of the adjustable delaycircuit of the frequency divider of FIG. 2.

FIG. 7 is a timing diagram of the frequency divider of FIG. 2.

FIG. 8 is a diagram of a phase locked loop utilizing the frequencydivider.

FIG. 9 is a flowchart of a frequency dividing method according to anembodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, electronic equipment manufacturers may refer to a componentby different names. This document does not intend to distinguish betweencomponents that differ in name but not function. In the followingdescription and in the claims, the terms “include” and “comprise” areused in an open-ended fashion, and thus should be interpreted to mean“include, but not limited to . . . ”. Also, the term “couple” isintended to mean either an indirect or direct electrical connection.Accordingly, if one device is coupled to another device, that connectionmay be through a direct electrical connection, or through an indirectelectrical connection via other devices and connections.

Please refer to FIG. 1, which is a block diagram of a frequency divideraccording to an embodiment of the present invention. The frequencydivider comprises a phase selector (PS) 120, an adjustable delay circuit140, and a controller 150. The phase selector 120 receives a pluralityof clock signals P0, P1, . . . Pn from a clock generator 100. Each ofthe clock signals P0, P1, . . . Pn has a predetermined amount of delaywith respect to the other clock signals. The predetermined amounts ofdelay may be , where T is period of the clock signals, N is number ofthe clock signals, and i=0,1, . . . ,(N−1). For example, for four clocksignals (N=4), the clock signal P1 may delay the clock signal P0 by 1/4T, the clock signal P2 may delay the clock signal P0 by 2/4 T, and theclock signal P3 may delay the clock signal P0 by 3/4 T, where T isperiod of the clock signals (the clock signals P0-Pn have substantiallythe same frequency). The phase selector 120 is capable of receiving theclock signals P0, P1, . . . Pn, and outputting an intermediate signalcorresponding to phase characteristic of at least one of the clocksignals P0, P1, . . . Pn based on a selecting signal. The adjustabledelay circuit 140 is for receiving the intermediate signal from thephase selector 120, and generating an output signal “Out”, such as adelayed clock signal, by delaying the received intermediate signal basedon a delay control signal. The controller 150 is for generating theselecting signal and the delay control signal, which are sent to thephase selector 120 and the adjustable delay circuit 140, respectively.Please note that, although the selecting signal and the delay controlsignal are provided by a single controller 150 in this embodiment, thisis not meant to be a limitation of the present invention; in otherembodiments, the selecting signal and the delay control signal may beprovided by different controllers, and the controller(s) may beintegrated within the phase selector 120 and the adjustable delaycircuit 140. Moreover, the selection function and the delay controllingfunction provided by the selecting signal and the delay control signalmay be predefined in the phase selector 120 and the adjustable delaycircuit 140; in this case, the selecting signal and the delay controlsignal may be omitted.

Please refer to FIG. 2, which is a diagram of the frequency dividershown in FIG. 1 according to one embodiment of the present invention. Inthe frequency divider shown in FIG. 2, N=4, i.e., four clock signals. Aclock generator 201 may be part of a phase-locked loop 200 that iscapable of outputting four clock signals P0, P1, P2, P3 that may delay areference clock signal by 0 T, 1/4 T, 1/2 T, and 3/4 T, respectively.The four clock signals P0, P1, P2, P3 may be received by a phaseselector 220. The phase selector 220 comprises four phase-characteristicselecting circuits 221 a, 221 b, 221 c, 221 d for receiving the clocksignals P0, P1, P2, P3, respectively. The phase-characteristic selectingcircuits 221 a-221 d may be flip-flop circuits. Eachphase-characteristic selecting circuit is controlled by a controller250, which outputs a selecting signal S0-S3 to the phase selector 220.For example, the controller 250 may control the phase-characteristicselecting circuit 221 b to select the phase characteristic of the clocksignal P1 representing a 1/4 T delay. In general, the clock generator201 and the phase selector 220 may account for up to (N−1)/N*T delay ofthe reference clock signal, in increments of 1/N. Thephase-characteristic selecting circuits 221 a, 221 b, 221 c, 221 dselectively output the phase characteristics of the clock signals P0,P1, P2, P3 according to the selecting signal S0-S3. Outputs of thephase-characteristic selecting circuits 221 a, 221 b, 221 c, 221 d aresent to a combining circuit 222, which may be implemented by logic gatessuch as logic OR gate, logic NOR gate, logic AND gate, and logic NANDgate, for combining the selected phase characteristics to generate anintermediate signal to an adjustable delay circuit 240. Each of theflip-flop circuits 221 a, 221 b, 221 c, 221 d may comprise two inputterminals for receiving one of the clock signals P0, P1, P2, P3 and theselecting signal S0-S3, respectively, and an output terminal foroutputting phase characteristic of the inputted clock signal when theselecting signal S0-S3 is enabled.

The adjustable delay circuit 240 may account for up to T/N delay (up to1/4 T delay in this embodiment) of the intermediate signal received fromthe phase selector 220, and is controlled by a delay control signalreceived from the controller 250. The delay control signal may controlthe adjustable delay circuit 240 to delay the intermediate signal by 0to 1/N times period of the clock signals, where N is number of the clocksignals. As shown in FIG. 2, the adjustable delay circuit 240 may be apipeline delay circuit comprising a plurality of delay units 241 a, 241b, . . . , 241 n whose delay amounts are controllable by the delaycontrol signal. First latches 242 a, 242 b, . . . , 242 n, logiccircuits 244 a, 244 b, . . . , 244 n, and second latches 246 a, 246 b, .. . , 246 n form control circuits for the respective delay units 241 a,241 b, . . . , 241 n for delaying the intermediate signal received fromthe phase selector 220 according to the delay control signal receivedfrom the controller 250. FIG. 3 shows another embodiment of the pipelinedelay circuit 240, while FIG. 4-6 show other embodiments of theadjustable delay circuit 240. The pipeline delay circuit shown in FIG. 3comprises a plurality of delay units 301 a, 301 b, . . . , 301N, aplurality of selection logic circuits (SL) 302 a, 302 b, . . . , 302N,and a plurality of latch circuits (LAs) 303 a, 303 b, . . . , 303N. Thedelay unit 301 a receives an input signal, e.g. the intermediate signal,and outputs a delayed signal O1 to the delay unit 301 b. After beingdelayed by the delay units 301 a, 301 b, . . . , 301N, the delay unit302N finally outputs a delayed intermediate signal OUT. The adjustabledelay circuit shown in FIG. 4 comprises a plurality of delay circuits401 a, 401 b, . . . , 401N, and a plurality of selection circuits 402 a,402 b, . . . , 402N. The selection circuit 402 a receives an inputsignal IN and a delayed input signal outputted by the delay circuit 401a, and is controllable by a selection signal SEL[0] for selectivelyoutputting either the input signal IN or the delayed input signal to thefollowing selection circuit 402 b and the following delay circuit 401 b.By controlling each of the selection circuits 402 a, 402 b, . . . , 402Nto select a delayed signal or a non-delayed signal, the adjustable delaycircuit shown in FIG. 4 may provide different delay times for delayingthe input signal IN to generate the output signal OUT. The adjustabledelay circuit shown in FIG. 5 may be considered a binary-controlleddelay line, and comprises a plurality of selection circuits 502 a, 502b, . . . , 502N, as well as a plurality of delay circuits 501 a[1], 501b[1], 501 b[2], . . . , 501N[1], 501N[2], . . . , 501N[2̂N]. Operationof the adjustable delay circuit shown in FIG. 5 is similar to operationof the adjustable delay circuit shown in FIG. 4. However, utilization ofthe selection signals SEL[0], SEL[1], . . . , SEL[N] in the adjustabledelay circuit of FIG. 5 results in binary control of the delay time. Forexample, for N=3, the delay time may range from zero to fifteen times aunit delay of each delay circuit. For SEL[0]=1, SEL[1]=0, SEL[2]=0, andSEL[3]=1, the output signal OUT lags the input signal IN nine times theunit delay. The adjustable delay circuit shown in FIG. 6 includes aplurality of delay circuits 601 a, 601 b, . . . , 601N, a plurality ofload circuits 602 a, 602 b, . . . , 602N, and a plurality of selectioncircuits 603 a, 603 b, . . . , 603N. The selection circuits 603 a, 603b, . . . , 603N may couple or decouple the load circuits 602 a, 602 b, .. . , 602N from the delay circuits 601 a, 601 b, . . . , 601N,respectively, so as to selectively delay in the input signal IN.Coupling the load circuit adds a delay, and each load may be adjusted toprovide different delay characteristics for the adjustable delay circuitof FIG. 6.

Please refer to FIG. 7, which is a timing diagram of the frequencydivider of FIG. 2. The timing diagram in FIG. 7 represents one exampleof operation of the frequency divider of FIG. 2. As shown in FIG. 7, theclock signal P0 is first selected. Thus, the controller 250 activatesthe selecting signal S0 corresponding to the flip-flop circuit 221 a anddeactivates the selecting signals S1-S3 corresponding to the flip-flops221 b-221 d. The selecting signal S0 enables the flip-flop circuit 221a, which activates the flip-flop circuit 221 a to output a latch signalA0 corresponding to the phase characteristic of the clock signal P0.While the selecting signal S0 enables the flip-flop circuit 221 a, theflip-flop circuits 221 b, 221 c, 221 d may be disabled, such that latchsignals A1, A2, A3 are inactive. The combining circuit 222 outputs theintermediate signal B having a phase corresponding to the phase of theclock signal P0.

The adjustable delay circuit 240 then delays the pulses of theintermediate signal B to generate an output signal OUT having a periodequal to (T′+ΔT). As shown in FIG. 7, the delay amount of theintermediate signal B increases by ΔT. When the delay amount equals T/4or is going to exceeds T/4, the controller 250 turns to enable theflip-flop circuit 221 b and disable the flip-flop circuit 221 a in orderto make the intermediate signal B have the phase characteristic of theclock signal P1, which is a T/4 delay of the clock signal P0.

The latch signal A1 outputted by the flip-flop circuit 221 b is receivedby the combining circuit 222, which outputs the latch signal A1 as theintermediate signal B. Similarly, the adjustable delay circuit 240delays the pulses of the intermediate signal B by ΔT, 2ΔT, 3ΔT, etc., tokeep the output signal at the period (T′+ΔT). Then, once the delayamount equals T/4 or is going to exceed T/4, the controller 250 willturn to enable the flip-flop circuit 221 c and disable the flip-flopcircuit 221 b to make the intermediate signal B have the phasecharacteristic of the clock signal P2, which is a T/4 delay of the clocksignal P1 and T/2 delay of the clock signal P0. In this way, the clocksignal is frequency-divided as the output signal OUT. That is, the inputfrequency 1/T becomes 1/(T′+ΔT) at the output of the frequency divider.

In the above, the frequency divider shown in FIG. 2 is only oneembodiment. The number N of the frequency divider may be chosenaccording to design considerations. Number of the plurality of clocksignals may be N, and number of the plurality of phase-characteristicselecting circuits may be N. Number of flip-flop circuits in the phaseselector 120, 220, number of clock signals P0, P1, . . . , PN, andnumber of selecting signals S0, S1, . . . , SN all may be varied withoutleaving the teaching described above. Logic gates may be substituted forthe flip-flop circuits 221 a-221 d. Further, the clock generator 100,200 and the phase selector 120, 220 may account for more or less than((N−1)/N)T delay of the reference clock signal. Likewise, the adjustabledelay circuit 140, 240 may account for more or less than (1/N)T delay ofthe reference clock signal. The controller 150, 250 may be digital,analog, or mixed. The adjustable delay circuit 140, 240 may employarchitectures other than the architecture shown in FIG. 2-FIG.6.

Because the frequency divider shown in FIG. 1 and FIG. 2 utilizes thephase selector to accomplish 0 to (N−1)*T/N delay, the delay length ofthe adjustable delay circuit can be significantly reduced. For example,when N=4, a delay of 0- 3/4 T is first provided by the phase selector,the adjustable delay circuit only needs to provide a delay of 0- 1/4 T.The circuit complexity and area of the adjustable delay circuit isreduced, and the frequency divider therefore has a simplified circuitdesign, with reduced power consumption and area, as well as betterjitter performance.

Please refer to FIG. 8, which is a diagram of a phase locked looputilizing the frequency divider. The phase locked loop comprises aphase/frequency detector (PFD) 810, a charge pump (CP) 820, a loopfilter (LF) 830, a voltage-controlled oscillator (VCO) 840, and afrequency divider 850, such as the frequency divider shown in FIG. 1 andFIG. 2. The phase detector 810 detects a phase difference between areference signal Fref and an input signal, and generates a differencesignal indicating the detected phase difference. The filter 830 coupledto the phase detector 810 filters the difference signal to generate afiltered signal. The oscillator 840 coupled to the filter 830 generatesa plurality of clock signals based on the filtered signal. The frequencydivider 850 coupled to the oscillator 840 and the phase detector 810generates a frequency-divided signal based on the clock signals. Thefrequency divider 850 may comprise a phase selector and an adjustabledelay circuit. The phase selector receives the clock signals and outputsan intermediate signal corresponding to phase characteristic of at leastone of the clock signals. The adjustable delay circuit coupled to thephase selector receives the intermediate signal and generates thefrequency-divided signal by delaying the intermediate signal. The inputsignal corresponds to the frequency-divided signal. In the above, theoscillator 840 may be a ring oscillator. The phase locked loop may alsocomprise a controller coupled to the frequency divider 850. Thecontroller may control the phase characteristic selection of the phaseselector of the frequency divider 850 to generate the intermediatesignal, and may also control the delay of the adjustable delay circuitof the frequency divider 850 to generate the frequency-divided signal.

Please refer to FIG. 9, which is a flowchart of a frequency dividingmethod according to an embodiment of the present invention. Thefrequency dividing method comprises receiving a plurality of clocksignals (Step 900), generating an intermediate signal according to phasecharacteristic of at least one of the clock signals (Step 902), anddelaying the intermediate signal to generate a frequency-divided signal(Step 904). The step of generating the intermediate signal (Step 902)may comprise selectively outputting phase characteristics of the clocksignals according to a selecting signal, and generating the intermediatesignal by combining the selectively outputted phase characteristics. Theclock signals may have predetermined amounts of delay with respect toeach other. The clock signals may be generated by delaying a referenceclock signal by 0 to (N−1)*T/N, where N is number of the clock signalsand T is period of the reference clock signal. The step of delaying theintermediate signal to generate the frequency-divided signal (Step 904)may comprise delaying the intermediate signal by 0 to T/N.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A circuit, comprising: a delay unit, arranged to delay an inputsignal to generate a delayed signal; and a latch, arranged to latch adelay control signal for controlling a delay amount of the delay unit,wherein the latch has an input terminal receiving the delay controlsignal, an output terminal coupled to the delay unit, and a controlterminal receiving the delayed signal.
 2. A circuit, comprising: a delayunit, arranged to delay an input signal to generate a delayed signal;and a latch, arranged to latch a delay control signal for controlling adelay amount of the delay unit, wherein the latch is controlled by thedelayed signal so that the delay control signal is latched until thedelayed signal triggers the latch.
 3. A pipeline delay circuit,comprising: a first delay unit, arranged to delay an input signal togenerate a first delayed signal; a second delay unit, arranged to delaythe first delayed signal to generate a second delayed signal; a firstlatch, having an input terminal receiving a delay control signal, anoutput terminal coupled to the first delay unit, and a control terminalreceiving the first delayed signal; and a second latch, having an inputterminal coupled to the first latch, an output terminal coupled to thesecond delay unit, and a control terminal receiving the second delayedsignal.
 4. A pipeline delay circuit, comprising: a first delay unit,arranged to delay an input signal to generate a first delayed signal; asecond delay unit, arranged to delay the first delayed signal togenerate a second delayed signal; a first latch, arranged to latch adelay control signal for controlling a delay amount of the pipelinedelay circuit, wherein the first latch is controlled by the firstdelayed signal so that the delay control signal is latched until thefirst delayed signal triggers the first latch; and a second latch,arranged to latch an output of the first latch or the delay controlsignal for controlling the delay amount of the pipeline delay circuit,wherein the second latch is controlled by the second delayed signal sothat the output of the first latch or the delay control signal islatched until the second delayed signal triggers the second latch.